It is generally accepted that clock jitter below 200ps rms is inaudible; although there are some who claim to hear as little as 2ps. Most S/PDIF receivers have <200ps jitter. So, the question is: Why would a DAC designer deliberately increase clock jitter by orders of magnitude, as is the case with asynchronous reclocking, and why doesn’t anybody hear it?
Asynchronous reclocking interposes latches in between the S/PDIF receiver and the DAC chip to reclock the data, bit clock, and word clock signals. The presumed purpose is to reduce jitter but that is preposterous. Asynchronous reclocking actually increases jitter.
In simplest terms, a latch or flip-flop is a digital circuit with two inputs, CLK and D, and one output, Q. Whatever binary value is present on the D input when CLK changes from low to high, is transferred to the Q output and held there until the next low to high transition of CLK. Regardless of the timing of changes at the input D, the output Q will change only when CLK transitions from low to high.
The usual implementation of asynchronous reclocking connects the CLK inputs of three latches to the reclock oscillator, the three D inputs to the data, word clock, and bit clock outputs of the S/PDIF receiver, and the three Q outputs to the respective data, word clock, and bit clock inputs of the DAC chip. (In actual practice, the latches have to be doubled, making six latches in total, to avoid an undesirable phenomenon called the meta-stable state. Conceptually, each double latch operates as a single latch.)
Ideally, the sample clock should be exactly 44.1KHz and the period of each and every clock cycle should be exactly 1/44100 seconds. But all oscillators have jitter, some more than others. With 200ps rms jitter expected in the S/PDIF sample clock, most clock periods will be too long or too short by 280ps rms. With asynchronous reclocking, each sample period will be an integral number of reclock periods and will be too long or too short by as much as a full reclock period. Because the clocks are asynchronous, an integral number of reclock periods will never equal the desired sample period. Reclocking with 100MHz, as the Prometheus DAC does, increases sample clock jitter, as seen by the DAC chip, to more than 5.7ns rms. 5.7 nanoseconds is considerably larger then 200 picoseconds!
Forcing the sample clock to be an integral number of asynchronous reclock periods will increase the granularity of the clock jitter. Instead of 22.675736961ns, the sample period is either 22.67ns or 22.68ns, +/- a few picoseconds. As a result, the effective sample rate jumps between two different frequencies, 44.09KHz and 44.11KHz, with a very predictable pattern. When the sampling frequency changes so does the frequency of the reconstructed audio signal. In other words, the changing sample frequency modulates the frequency of the audio signal.
It’s like wow and flutter. Perhaps that’s why some listeners report that asynchronous reclocking sounds more ‘analog-like’, meaning it sounds like a cheap turntable. Pitch stability is one area where digital audio is superior to analog. Why negate that benefit with asynchronous reclocking?
One more thing: I think the Prometheus web site is a real hoot. They make a big deal that the “clock module is place below the PCB to prevent spraying the board with noise.” That’s nice, but chances are the clock module is a ready-made oscillator hermetically sealed in a metal box. It’s hard to imagine a better electrostatic shield. Meanwhile, the reclocking latch, which is directly clocked by the reclocking oscillator, is mounted on top of the PCB and located a few centimeters from the DAC chip. The latch is encapsulated in plastic and its long bond wires, which traverse the entire length if the chip package, act as antennas spraying the DAC chip with RFI. What’s more, the eight latches, clocked simultaneously with only single VCC and ground pins located at diagonal corners and the decoupling cap located at the wrong end of the chip, will produce considerable ground bounce, which will add significant noise to the ground plane.
I can’t tell from the photo but I’ll bet the reclocking latch is a 74AC374 or equivalent. The 74AC logic family is well known for ground bounce and noise. When 74AC was developed, ground bounce was not well understood. More recent CMOS logic families are specifically designed to minimize ground bounce and noise that plagued earlier high-speed logic.
If all you golden ears think the Prometheus DAC is the best you have every heard. What can I say? Ignorance is bliss. Enjoy.
