[Jye]

then the SRC of the chip is disabled with maximum frequencies supported?

I can't comment on how the ESS Sabre chip works internally, and whether there is a SRC in action within the Hyperstream architecture. We setup the chip such that PCM and DSD goes in the way it is from the source.

[giordy60]

I can't comment on how the ESS Sabre chip works internally, and whether there is a SRC in action within the Hyperstream architecture.

https://i.imgur.com/9Xxqtdi.png[/img]]

[giordy60]

...... We setup the chip such that PCM and DSD goes in the way it is from the source.

chip mapping can be changed ?
if so, you should know the signal path before and after the chip: scratch: