Hi Hugh/Tinker,
how do the DAKSA "jitter immunity/reduction" mechanisms compare to
http://www.benchmarkmedia.com/appnotes-d/whyultralock.asp
This has been getting favourable comment in some forums (At $1000 USD)so I wondered what the comparison from a technical viewpoint was ?,
I don't pretend to understand to any great degree the technical aspects of jitter and anti-aliasing filters but from an Engineering viewpoint the "buffering" concept in the DAKSA seems to actually solve most (all ? ) of the issues with jitter, so just wondering .
cheers and regards,
Ray
In short, I am not sure precisely what in happening inside one of these things. I do not want to create any friction by second-guessing a manufacturer or making claims about products I haven't acutally measured and tested myself. So this is a hypothetical discussion abot jitter reduction methods. The URL you posted had a description saying the conversion clock is not phase-locked to a reference clock (ie not a PLL), rather the converter oversampling-ratio is varied achieve phase-lock to the reference clock.
What this
sounds like is a high precision master clock on the DA with an asyncrhonous samplerate convertor probably a polyphase digital filter. I could be wrong. Maybe someone with one of these could open it up and tell us? In fact there was a thread about benchmark in pro-audio-digest. With permission I may try and post their results here.
Resampling or polyphsae filtering This is a workable approach to jitter reduction, and is a standard method of interfacing systems without having to actually synchronise clocks. If you want to read more about how these work, go to the analog device home page
http://www.analog.comand get the data sheet for the AD1896 asynchronous samplerate convertor. Document 71654447AD1896_a.pdf, I think. Let me kow what you think.
The DAKSA does not do any filtering of this kind. It uses a buffer and a predictive algorithm to decouple the transport and DAC clocks down to very low frequencies. If you like a "loose" PLL without the limitations of a low pass filter on the PLL loop filter. It is hoped (still subject to testing phase III!) that we can reduce jitter very close to the limits of the DAC master clock.
More later.
T.
