A chip converts USB to SPDIF, this in turn is fed into a receiver which takes all of the SPDIF inputs, then some reclocking magic to eliminate jitter, and finally to the DAC (which unless I'm wrong is always fed by an I2S signal at this point). Fueled by what I assume to be the promise of your products people seem to be calling this an inferior implementation. However, in looking at your USB to I2S products, they all seem to include turboclock or a similar clocking mechanism which leads me to believe there is no simple USB to I2S conversion chip which might eliminate clocking altogether. My ultimate question is this. Are the implementations in these two DAC's flawed, or is the main benefit of I2S the lack of jitter introduced in transmission, and thus the main difference between your products and theirs would be the method of reclocking the digital signal?
Elimination of clocking is impossible. There is always a clock that moves the data through the DAC chip. The issue is how much jitter is in this clock. Also, these circuits that "reclock" are never very effective. It takes a LOT of chips to sigificantly reduce jitter, and it will never happen with the S/PDIF signal.
In the USB to S/PDIF implementations, the clock is encoded with the data in the S/PDIF datastream. Then it requires a "receiver" chip to recover the original clock from the S/PDIF datastream. This clock recovery from the datastream is what results in a lot of jitter. This recovered clock from the receiver chip is then sent to the DAC chip, which MUST have a clock. The clock is generated by the "receiver" chip. Therefore, there are three chips minimum involved, the USB to S/PDIF chip, the Receiver chip and the DAC chip, along with buffers. This also requires a master clock oscillator that drives the USB to S/PDIF chip so that it can communicate on the USB bus and encode the clock and data into the S/PDIF signal.
In the USB to I2S implementations, the clock is generated in the USB to I2S conversion chip. It is never encoded in the data. Therefore, the jitter in this clock will be much lower. There is still a master oscillator that drives the USB to I2S chip. This is where the Superclock comes in. The clock that is generated by the USB to I2S conversion chip goes directly to the DAC chip. Only two chips are involved, the USB to I2S and the DAC chip, along with buffers. It is the fewer chips and the fact that there is no encoding and decoding of the clock with the data that makes the jitter much lower. This is why I2S is superior.
I am also designing a new circuit that works only with the computer and USB to I2S interfaces, that will result in extremely low jitter. This device I call the "Pace-Car". It will be included in my new USB DAC that I plan to debut at 2007 CES. I may also offer it as an external box that inserts between the Off-Ramp I2S and the I2S DAC. This device will generate the master clock and send a clock back to the Off-Ramp I2S. The Off-Ramp I2S will not need a local clock (superclock) because it will now come from the Pace-Car. This is sort of like the "word-clock" concept used with some DAC's, only different, and hopefully better.
Steve N.
