dac 10 and SRC

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Jye

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Re: dac 10 and SRC
« Reply #20 on: 11 Apr 2018, 05:16 am »
then the SRC of the chip is disabled with maximum frequencies supported?

I can't comment on how the ESS Sabre chip works internally, and whether there is a SRC in action within the Hyperstream architecture. We setup the chip such that PCM and DSD goes in the way it is from the source.

giordy60

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Re: dac 10 and SRC
« Reply #21 on: 13 Apr 2018, 11:25 am »
I can't comment on how the ESS Sabre chip works internally, and whether there is a SRC in action within the Hyperstream architecture.

https://i.imgur.com/9Xxqtdi.png[/img]]

giordy60

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Re: dac 10 and SRC
« Reply #22 on: 16 May 2018, 12:12 pm »
...... We setup the chip such that PCM and DSD goes in the way it is from the source.

chip mapping can be changed ?
if so, you should know the signal path before and after the chip: scratch: